Verilog Localparam?

Question

What are localparams in Verilog and how do I use them?

Answer 1

The localparam in Verilog is a kind of constant that is local for modules and available only inside the module in which it is declared. I use it to define some module-specific implicit parameters and settings that are for module use only and doesn't specify it's behavior for external configuration (regardless of what it actually is).

For example, I can define a global parameter of address bus width and then I derive from that value either the buffer depth or the number of registers. For any external devices it doesn't matter what it actually is inside my module.

Examples:

CAPTURE_CLOCK_MUL_FACTOR - is the parameter form a module declaration

  localparam CAPTURE_CNT_WIDTH = $clog2(CAPTURE_CLOCK_MUL_FACTOR);
  logic [CAPTURE_CNT_WIDTH-1:0] capture_cnt = {(CAPTURE_CNT_WIDTH){1'b0}};
  localparam vote_pos_1 = CAPTURE_CLOCK_MUL_FACTOR / 3 - 1;
  localparam vote_pos_2 = CAPTURE_CLOCK_MUL_FACTOR / 2 - 1;
  localparam vote_pos_3 = CAPTURE_CLOCK_MUL_FACTOR / 2 + 1;

  reg state;
  localparam stHead = 1;
  localparam stBody = 2;
  localparam stTail = 4;

Answer 2

If you want to create a parameter and make sure that its value is not accidentally changed somewhere along the program, you use 'localparam'. Localparam is same as 'parameter' but unlike 'parameter', its value cannot be modified by redefinition or by the keyword defparam. However, local parameters can be assigned to parameters that can, in turn, be modified. Relevant examples are given as:

parameter Width = 8;
localparam Depth = Width*12;
localparam Size = 16;