Interested In VHDL Training? Click Here

0 votes
in Verilog by (240 points)

What is a generate statement in Verilog and how do I use it?

2 Answers

0 votes
by (220 points)

Generate statements is the Verilog construction that is used to either conditionally or instantiate multiple generate blocks into a model. A generate block is a collection of one or more module items. This is a powerful tool for parameterizing and configuring the module's architecture and of simplifying its implementation. I use it to create a needed IP cores set, to configure a set of modules, to scale a homogenious structure, to select either a data processing algorithm or protocols etc.

There are two kinds of generate statement constructions: loops and conditionals. The loop generate statement allows a single generate block to be instantiated into a model multiple times. The conditional generate statement includes an either if-generate or case-generate construct and instantiate at most one generate block from a set of alternative generate blocks. All these blocks can nest and branch. Any if-genearte block may include other if-generate blocks, case-generate blocks or loop generate blocks and vice versa in many various combinations

The keywords generate and endgenerate may be used (and is better to use it) in a module to define a generate region. A generate region is a textual span in the module description where generate constructs (or statements) may appear.

Example:

generate
if (index_cnt_delay > 1) begin //
always @(posedge clk_i) index_cnt_line <= {index_cnt_line[index_cnt_delay-2:0], index_cnt[5:0]};
end
else begin
always @(posedge clk_i) index_cnt_line[0] <= index_cnt[5:0];
end
endgenerate
0 votes
by (220 points)

There are two kinds of generate statements: generate loops and conditional generate. Genrealized syntax of generate statement is given as:

generate 
[ genvar_declaration ]
generate_scheme
generate_block
endgenerate
Genvar is a variable and the index used for the generate statement. The index tells us the number of times the block will be generated. Generate scheme indicates whether it is a generate loop or conditional generate.

Example code of a loop generate is given as:
generate
genvar i;
for (i = 0; i < 10; i = i + 1)
begin : gen
initial $display("%d", i);
end
endgenerate
An example code for a conditional generate is:
generate
if (A < B)
Mult1 u1 (A, B, Q);
else
Mult2 u1 (A, B, Q);
endgenerate

Want to improve your VHDL skills?

Click Here - Sign Up For VHDL Training

© 2022 by Hardware Coder. User contributions are licensed under cc by-sa 4.0 with attribution required. Attribution means a link to the question, answer, user, etc on this site.

This site is owned and operated by Hardware Coder in McKinney, Texas.

Send Us A Message
About Us

By using this site, you agree to the following:

Privacy Policy
Terms and Conditions
DMCA Policy
Earnings Disclaimer
Legal Disclaimer

...