# Verilog Operators?

in Verilog

What are Verilog operators and how do I use them?

by (200 points)

Operators are identifiers that contain 1,2, or 3 symbols (in Verilog) and defines an arithmetical, logical, equational, bit-wise, and conditional operation in expressions. So Verilog operators are: arithmetic, logical, equational, bit-wise, and conditional. Also operators are unary operators and binary operators. Unary operators appear to the left of their operand. Binary operators appear between their operands.

{} {{}} - Concatenation, replication: assign {a, b} = {{(10){1'b0}}, c}; // the result size must be the size of a + the size of b
? : - Conditional: a <= condition ? 1'b1 : alternative_a;

Arithmetic:

binary:
+ - * / ** - addition, subtraction, multiplication, division, power
% - modulus

unary:
unary + unary - - Unary operators. Are for sign.

Logical:
! - Logical negation: if ((!a && b) || c)
&& - Logical and
|| - Logical or

Equational:
> >= < <= - Relational: assign a = b >= c; if (a < b)
== - Logical equality: a <= c == b ? d : e;
!= - Logical inequality: c = a != b
=== - Case equality: if (a === 1'bx)
!== - Case inequality

Bit-wise:

binary:
~ - Bitwise negation: q <= ~a ; // if a = 0101, then q = 1010
& - Bitwise and: c = a & 8'h3e; // if a = 7c, then c = 3c
| - Bitwise inclusive or: assign c = a | b;
^ - Bitwise exclusive or: assign sum = a ^ b;
^~ or ~^ - Bitwise equivalence: wire eq; wire [3:0] a; assign eq = a ^~ 4'ha;
<< - Logical left shift: q = (a >> src_pos) << tgt_pos;
>> - Logical right shift
<<< - Arithmetic left shift: the sam as <<
>>> - Arithmetic right shift: reg [3:0] r = 4'ha; r >>> 2 the same as >>, but \$signed(r) >>> 2 is 4'b1110

unary:
& - Reduction and: &a // will be 1 only if all bits of a are 1;
~& - Reduction nand: ~&a // will be 0 only if all bits of a are 1;
| - Reduction or: |a // will be 1 if any of bits of a is 1;
~| - Reduction nor: ~|a // will be 0 any of bits of a is 1;
^ - Reduction xor: ^a // will be 1 only if "a" has an odd number of bits equal to 1
~^ or ^~ - Reduction xnor: ~^a // will be 1 only if "a" has an even number of bits equal to 1

by (220 points)

There are a variety of operators in Verilog that perform various operations on operands. Arithmatic operators perform arithmatic operations like addition, subtraction, multiplication and modulus. The five arithmatic operators are given in the code snippet below (assume the variables are declared in the module):

begin
Y2=A-B;//subtraction
Y3=A*B;//multiplication
Y4=A/B;//division
Y5=A%B;//modulus of A divided by B
end
Relational operators compare two variables/operands and returns whether the relation is true or false. They are used in conditional expressions. These operators are shown below along with one example of their use in an 'if-statement'.
begin
Y1=A<B;//less than
Y2=A<=B;//less than or equal to
Y3=A>B;//greater than
if (A>B)
Y4=1;
else
Y4=0;
end
Sign operator can be used to assign a postive (+) or a negative(-) sign to a variable. If no sign is assigned, it is automatically assumed that the variable is positive.

Furthermore, there are equality and inequality operators. These are different from assignment operators. They are used for conditional expressions and compare values of two parameters and return a true or false. For example A==B returns 1 if A is equal to B and 0 otherwise. Similarly A!=B is the inequality operator and this expresssion returns 1 if A is not equal to B.

Conditional expressions sometimes also use logical operations for comparison of two parameters. These logical operators are logical OR and Logical AND. Logical OR is performed by the operator: ||, while logical AND is performed by the operator &&. Notice that the comparison operation is different from bit wise operation, in which case OR is done by a single | and AND operation is performed by single ampersand &. Bit-wise XOR is performed by the operator ^.

If ~ sign preceeds any bitwise operation, it means it is performing the inverting fucntion. NOR is done by ~|, NAND is done by ~& and XNOR is done by ~^.