Verilog Random?

Question

How do I create a random in Verilog?

Answer 1

Verilog HDL has a simple set of pseudorandom generator functions: $random[(seed)], $srandom[(seed)], $urandom[(seed)], $random_range().

$srandom - to generate signed numbers,
$urandom - unsigned..
$random_range() is to generate numbers in given range. Also for ranging %: ($random % border) - the result must be in the range of [(-border+1):(border+1)]

`timescale 1ns / 1ps

module tb();

  reg clk = 1'b0;
  always #10 clk = ~clk;

  reg signed [7:0] a = -128, b = -128;
  wire signed [8:0] c;

  always @(posedge clk) begin
    a <= $random % 128; 
    b <= $random % 128;
    $strobe("A = %d, B = %d, A - B = %d", a, b, c);
  end

  subtractor dut (a, b, c);

endmodule

Answer 2

The command $random generates random number in verilog. It returns a 32 bit signed integer. To restrict the number in a particular range use the command as follows:
$random % b
This command will generte a random number in the range [(-b+1):(b-1)]
For example: $random % 2 generates a random number in the range [-1,1]