Register File Verilog?

Question

What is a register file in Verilog and how do I use it?

Answer 1

1. If you are asking about a CPU register file.
A register file is an array of processor registers in a CPU. It is used by the CPU to fetch and hold the data from the secondary memory devices. It is placed right within the CPU so it is much faster than the other memory devices.
Verilog doesn't have any dedicated construction for this and this may be only coded in various ways.

The simplest one:

module reg_file #(
  parameter NUMBER_OF_REGISTERS = 32,
  parameter DATA_WIDTH = 32
)(
  input rst,
  input clk,
  input wr_en,
  input rd_en,
  input [$clog2(NUMBER_OF_REGISTERS)-1:0] rd0_addr,
  input [$clog2(NUMBER_OF_REGISTERS)-1:0] rd1_addr,
  input [$clog2(NUMBER_OF_REGISTERS)-1:0] wr_addr,
  input [DATA_WIDTH-1:0] wr_data,
  output reg [DATA_WIDTH-1:0] rd0_data,
  output reg [DATA_WIDTH-1:0] rd1_data
);

  reg [DATA_WIDTH-1:0] mem [0:NUMBER_OF_REGISTERS-1];
  integer i;

  always @(posedge clk) begin
    if (rst) begin
      for (i=0; i<4; i=i+1) mem[i] <= {(DATA_WIDTH){1'b0}};
    end else if (wr_en) begin
      mem[wr_addr] <= wr_data;
    end        else if (rd_en) begin
      rd0_data <= mem[rd0_addr];
      rd1_data <= mem[rd1_addr];
    end
  end

endmodule

Or you can use either a memory or matrix model (how it probably would be if you designed it for ASIC).

2. If you are asking about loading a file data into the memory, this is done by $readmemb and $readmemh system tasks.

Syntax:

load_memory_tasks ::=
$readmemb ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;
| $readmemh ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;

Example:

  logic [12:0] coarse_table [0:2**10-1];
  logic [3:0] fine_table [0:2**9-1];
  task InitSineTables();
    begin
      $readmemb("coarse_bin.txt", coarse_table);
      $readmemb("fine_bin.txt", fine_table);
    end
  endtask

Answer 2

Data from secondary memory devices is held within CPU in a register file. It is a memory space in the CPU. Details of its ports are given below:

Input(IP1): 32 bit
Outputs (OP1 and OP2): 32 bit each
Clock (clk): 1-bit
Enable (EN): 1-bit
Reset(rst): 1-bit
Input select (sel_i1): 4-bit
Output selects( Sel_o1 and Sel_o2): 4 bit each
Read (RD): 1-bit
Write (WR): 1-bit

During the write operation, value given at the input select port is used to select the register in which data from the input port will be stored. During read operation, values in the output select port are used to select the register from which values are sent to output ports.

Verilog code for register file is given below (https://esrd2014.blogspot.com/p/register-file.html):

module regFile( Ip1,
sel_i1, 
Op1,
sel_o1, 
Op2,
sel_o2, 
RD,
WR, 
rst,
EN, 
clk
); 

input [31:0] Ip1; 
input [3:0] sel_i1,
sel_o1,
sel_o2; 
input RD,
WR; 
input EN,
clk,
rst; 
output [31:0] Op1,
Op2; 
reg [31:0] Op1,
Op2; 
reg [31:0] regFile [0:15]; 
integer i; 
wire sen; 
assign sen = clk || rst; 
always @ (posedge sen) 
begin 
if (EN == 1) 
begin 
if (rst == 1) //If at reset 
begin 
for (i = 0; i < 16; i = i + 1) begin
regFile [i] = 32'h0; 
end 
Op1 = 32'hx; 
end 
else if (rst == 0) //If not at reset 
begin 
case ({RD,WR}) 
2'b00: begin 
end 
2'b01: begin //If Write only 
regFile [sel_i1] = Ip1; 
end 
2'b10: begin //If Read only 
Op1 = regFile [sel_o1]; 
Op2 = regFile [sel_o2]; 
end 
2'b11: begin //If both active 
Op1 = regFile [sel_o1]; 
Op2 = regFile [sel_o2]; 
regFile [sel_i1] = Ip1; 
end 
default: begin //If undefined 
end 
endcase 
end 
else; 
end 
else; 
end 
endmodule

Answer 3

Register file likes the 2D, 1D array register. But we can initialize the value of them. And can use the Block ram to replace in case it's larger to use.