Verilog D Flip Flop?

Question

How do you code a d flip flop in Verilog?

Answer 1

The D flip-flop actually is a modification of the clocked SR flip-flop. The D input goes into the S input and the inverted D input goes to the R input. The D input is sampled by a clock pulse. If it is 1, the flip-flop is switched to the set state (Q -> 1). If it is 0, the flip-flop switches to the reset state (Q -> 0). In simple terms, the D flip-flop is just the sampled d input by the clock edge.

module dff (
  input clk,
  input d,
  output q,
  output qn
);

  reg ff;

  always @(posedge clk) ff <= d;

  assign {q, qn} = {ff, ~ff};

endmodule

Answer 2

It is a basic memory cell that is triggered when an active edge transitions occurs. At the rising or falling edge of the clock signal, depending on the design, the value at the D-input of the flipflop is captured and it appears on the output Q. The value is held until the next transition of the clock. An example code of a postive edge or rising edge D-Flip Flop is shown below (source: https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html):

module RisingEdge_DFlipFlop(D,clk,Q);
input D; // Data input 
input clk; // clock input 
output Q; // output Q 
always @(posedge clk) 
begin
Q <= D; 
end 
endmodule

The code for the falling edge or negative edge D-Flip Flop is the same except the key word 'posedge' is replaced with 'negedge'.

Answer 3

Here is an example of D_FF with synchronous reset. The reset value is zero by using constant in verilog.

parameter RESET_VALUE = 1'b0;
reg d_ff;
always @(posedge clk)
     begin
     if(rst) d_ff <= RESET_VALUE;
     else d_ff <= in_dat;
     end