Verilog Repeat?

Question

What is repeat in Verilog and how do I use it?

Answer 1

Executes a statement a fixed number of times. If the expression evaluates to unknown or high impedance, it is treated as zero, and no statement is executed.

repeat (5) begin
  #10us;
  i_data = 77;
  @(negedge i_clk) i_en_str = 1;
  @(negedge i_clk) i_en_str = 0;
  @(posedge o_done);
  speed = 434 * 2;
end

repeat (64) begin
  @(posedge isys.clk);
  iuart_tx.data[15:8] = 8'h80 | (operation_index + start_position) % 64;;
  iuart_tx.data[7:0] = aes3_to_i2s_test_info.registers_expected[(operation_index + start_position) % 64];
  if ((operation_index + start_position) % 64 == 0) iuart_tx.data[7] = 1'b0; 
  while (iuart_tx.busy) @(posedge isys.clk);
  iuart_tx.enstr = 1'b1;
  @(posedge isys.clk);
  iuart_tx.enstr = 1'b0;
  @(posedge iuart_tx.done);
  operation_index++;
end

Answer 2

The repeat statement is used to run a selected portion of code a specific number of times. It is similar to a for-loop. The difference is that there is no condition and the index is not used inside the loop. Repeat loop is used when we simply want to run a portion of code repeatedly for a fixed number of iterations. Example is given below:

module repeat_example (); 
reg r_Clock = 1'b0;
initial
begin
repeat (10)
#5 r_Clock = !r_Clock;
$display("Simulation Complete");
end
endmodule

Answer 3

This is one of the loop statements of Verilog, and is usually used in testbench design. In case we would like to repeat the statement on how many times we want.