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in Verilog by (220 points)

What is the difference between a wire and a reg in Verilog?

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by (220 points)

The Verilog reg is the object that can store a value and a drive strength. It may be used for designing both a combinational and a sequential logic - doesn't matter, the main thing is that reg is a storage object. This is the main difference with a wire, which is actually is a wire that connects points. And these points may be determined as either explicit or implicit objects of reg data type. The data of type reg can only be driven in initial and always blocks. So if we need to specify either sequential logic (flip-flops) or complicated combinational logic (which would be hard to fit in continuous assignments) - we'll use the reg.

The data of type wire can only be driven in continuous assignment. And each module can be represented as a set of multiple modules that incapsulates sequential and/or combinational logic which is specified with using data/variables of type reg, and that are connected by nets of type wire by using continuous assignments.

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Wires are used in combinational logic while registers (reg) can be used in combinational as well as sequential logic. Reg declaration is used inside a behavioural statement such as 'initial' and 'always'. Wire is used for simple assignment and is not used for sequential logic. Keyword 'assign' is not used with reg.

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by (220 points)

The wire and the reg are two basic types in Verilog. The wire is declared and use with its value updated immediately (combination logic). And the register value is updated on the active edge of clock. Each logic when going through the register will be retimed, it's better for the timing score in digital design.

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