# Verilog 2d Array?

in Verilog

How do I use 2d arrays in Verilog?

by (200 points)

Even the Verilog standard have no strictly defined understanding of what is a 2d array. This is from standard:

reg [7:0] mema[0:255]; // declares a memory mema of 256 8-bit registers. The indices are 0 to 255
reg arrayb[7:0][0:255]; // declare a two-dimensional array of one bit registers
wire w_array[7:0][5:0]; // declare array of wires
integer inta[1:64]; // an array of 64 integer values
time chng_hist[1:1000] // an array of 1000 time values
integer t_index;

But later 'wire [SIZE-1:0] t [1:3];' have became a two-dimensional array too.

I think that a 2d array is 'reg arrayb[7:0][0:255];' because if range is placed before the name - it is a vector.
I've used 2d arrays for scaling homogenious structures by using for-generate statements but very rarely. In most cases I use 1d arrays of vectors, as for data buses of channels, memories, homogenious outputs of multiple modules instances, etc.

``  wire [1599:0] round_rin_half_0_net [0:12], round_rout_half_0 [0:12];  assign round_rin_half_0_net[0] = {65'h0, 8'h80, 400'h0, 8'h6, nounce_i};  assign state_o = round_rin_half_0_net[12];  ...   genvar i, k; ...generate  for (i = 0; i < 12; i = i + 1) begin    reg [1599:0] round_rin_reg;    round_logic #(.USE_CARRY(0), .USE_CHI_RTL(0), .INPLICIT_PIPELINE(LOGIC_ROUNDS_INPLICIT_PIPELINE), .THETA_REGISTER(THETA_REGISTER)) round_inst(      .clk_i(clk_i),      .rc_i(rc[(23-i)*64+:64]),      .state_i(round_rin_half_0_net[i]),      .state_o(round_rout_half_0[i])    );  end ....endgenerate``
by (240 points)

2D array declaration is simple in verilog:

reg a[7:0][3:0]

This line of code creates a 4x8 2D array. Multiple bits can be stored in an element of an array in verilog. For instance:

reg [3:0] array1[7:0][3:0]

The 2D array array1 stored 4-bit data in each of its elements. A simple code is given below to illustrate how to store values in a 2D array:

``reg [7:0] b [0:3] [0:3];initial begin// using 2Dfor (int i=0; i<=3; i++)for (int j=0; j<=3; j++)b[i][j] = i*j; // watch this if you're building hardwareend``
``always @(posedge clk) in_data[0][7] <= 1'b1; //assign the bit 7 of register array 0 = 1``