Verilog Signed

Question

How do you use $signed in Verilog?

Answer 1

The keyword signed is used to declare Verilog object data types as signed types. This is for better modelling a signed arithmetic when the MSB is assumed as the sign bit. I usualy don't use this and just code according with binary arithmetic rules but sometimes it is useful for avoiding mistakes. Also, Verilog makes a sign extension for objects of different sizes that are declared as signed.

Also there is $signed system function to cast a data as a signed data type. Example:

  wire signed [7:0] a, b;
  wire signed [8:0] c;
  assign c = a - b;

Actually, I can do the same by using just wire without 'signed' but the use of 'signed' makes it little more explicit. Also, signed is needed when want to use the >>> operator for an arithmetical shift right.

Answer 2

Default declaration in verilog is unsigned. If a signed variable needs to be declared then the signed keyword is used. Example declarations are given below:

reg signed [7:0] A;
wire signed [7:0] B;
input signed [15:0] C;

If we want to return a signed value of some specific operation or if we want any variable to be treated as signed during any specific operation then $signed is used. For example, consider the code given below:

wire [7:0] a; 
wire [7:0] b; 
wire less; 
assign less = ($signed(a) < $signed(b));

It is the same as the code below:

wire signed [7:0] a; 
wire signed [7:0] b; 
wire less; 
assign less = (a < b);

Answer 3

Of course, we can declare the variable as a sign type, but the best way to use a sign signal is self-control. That means we need to separate the sign and the value to control for each operation.