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in Verilog by (220 points)

What is $monitor in Verilog and how do I use it?

3 Answers

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by (240 points)

$monitor displays text on the screen during simulation every time one of its parameters change. Example:

$monitor("left channel state flag is %d,\nright channel state flag is %d", left_channel_state_flag, right_channel_state_flag);

It would be better to use it for logging changes of needed objects that aren't changed at a high frequency.

0 votes
by (200 points)

The monitor statement is a system task and is ignored by the synthesis tool. It is used to monitor values for verification. It diplays the values of its parameters whenever there is a change. The syntax is given below:

$monitor ("format_string", parameter1, parameter2, ... );

The 'format string' specifies the format in which the values must be displayed. For displaying values in decimal "%d" is used. For displaying values in hexadecimal format "%h" is used and "%b" is used for binary representation.

If you want to display 4-bit binary number you use "%4b". For example:

$monitor("a=%2b,b=%2d,c=%b \n",a,b,c);

The above given code diplays the variable 'a' as 2-bit binary number, the variable 'b' as 2 digit decimal number and the variable 'c' as 1 bit binary number.

0 votes
by (200 points)

The monitor function is usually used in testbench design. Its like the printf in C language but it just shows the value once the value of variable monitor changed. And when we use it in the Simulation environment, it will be dumped in the log file.

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