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in Verilog by (220 points)

How do you use constants in Verilog?

3 Answers

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by (200 points)

There are constant numbers in the Verilog Standard that are specified as integer constants or as real constants. Integer constants may be defined as either a simple decimal value or based constant (an optional size constant, an apostrophe character (', ASCII 0x27) followed by a base format character, and the digits). Examples:

1, 10, 127, 16'habcd, 3'b001, 4'd9

The real constants represent floating point values and are defined in either decimal notation (for example, 14.72) or in scientific notation (for example, 39e8). I use it directly in expressions and equations where its meaning is clear, or if its not clear, I use it through local params.

On the other hand I prefer to understand these constants as literals, but localparams and parameters as constants. I use it for:

- setting arrays ranges (for buses, counters, memory width and depth, register's width etc, pipeline width and size),
- configuring module's architecture by using generate statements that include any homogenious structures (I can define a number of repeats), other module instances, IP-cores, specific implementation etc.
- as a named constant value for computations, FSM implementations and so on (also to avoiding magic numbers)

0 votes
by (240 points)

Integer Constants can be defined as sized or unsized numbers. The general format is:

sign size 'Base number

For example, -5'b_1001 means a negative binary number of five bits with a value equal to 01001. Underscore is ignored and it is used to simply increase readibility of the code. Similarly, for a decimal constant, 'd is used as a base identifier and for a hexadecimal constant, the 'h identifier is used. If size and base are not mentioned then by default it is a positive decimal number. Some examples of contants are given below:

10 'd 21
8'h z
6'o 72

Floating point constants are defined using digits, underscores, decimal points and exponential symbols only. Base idetifier and size is not mentioned. Decimal or scientific notation is used to specify real constants:


0 votes
by (240 points)

There are two types of constant in Verilog, one is localparam and one is parameter:

- localparam: just use in the module that we clear it.
- parameter: we can re-config the value from the higher module.

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