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in Verilog by (220 points)

What is a sign extend in Verilog and how do I use it?

3 Answers

0 votes
by (200 points)

The sign extension is filling the leftmost bit by a sign bit if operands have different sizes. In Verilog, it is only if all operands are signed. If you want a signed arithmetic with an ability to have a sign extension then you need to declare all operands as objects of the signed data types, or use $signed();

reg signed [7:0] a;
reg [5:0] b = 6'h30; // will be a negative
c = a + $signed(b);
Or you can do this: c = a + $(signed({1'b0, b}) so the right operand is positive.

Or you could do something like this: c = a + {{2{b[5]}}, b}; or c = a + {2'b00, b};

Also you can do this with localparams and/or parameters if data sizes are fixed and are knowns.
0 votes
by (200 points)

Sign extension is done when the number of bits are increased and the sign needs to be preserved. The most significant bit is copied to the higher bits that are added to the original number. If all operands are declared as signed type then verilog automatically sign extends these variables during any operation that needs alteration in the number of bits of the operands.

Unsigned numbers are zero extended and not sign extended. If your variable is unsigned and you want to sign extend it in any expression, use the $signed command. It converts the variable to signed variable.

For example if a variable, a, is originally unsigned, it can be converted to signed in an expression by:


0 votes
by (240 points)

We can declare the variable with a sign extend, and the sign will be the value of the MSB of this variable:

1: negative
0: positive.

But we need to be careful when using sign extends the operation and make sure all of the variables is sign extended also if one of them is not sign extended, the operation is not sign extend to, and the sign bit will be the value bit.

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