Verilog Ifdef?

Question

What is ifdef in Verilog and how do I use it?

Answer 1

Its the conditional compilation directive that is used to include either optional or alternative lines of Verilog HDL source description during compilation.

The `ifdef checks for the definition of a macro. If it is defined, then the lines following the `ifdef are included. If the macro is not defined and an `else directive exists then it includs what is following the `else. The `ifndef compiler directive does the same as `ifdef but for when the macro is not defined. The `elsif directive is a combination of `else and `ifdef. The `endif is borders the lines of code that are controlled by the `if(n)def.

`ifdef USE_EXTRA_TRIGGER_P45
`ifdef USE_NEGDEDGE
  always @(negedge clk_i)
`else
  always @(posedge clk_i)
`endif
  out45_extra <= out45;
  assign clk_o_net = out45_extra;
`else

`ifdef USE_Q2
  assign clk_o_net = q1;
`else                
  assign clk_o_net = out45;
`endif
`endif

Answer 2

When an ifdef is used, the compiler will check if the macro is defined before. If it is defined, the define code will be subsituted, but if not defined or if there is else or elsif it will be ignored.