in Verilog

What is a carry look ahead adder and how do I code it in Verilog?

by (240 points)

In ripple carry adders the result delay is defined by a propagation delay of all carry line from the cin to the cout. This is if it is not pipelined. A carry-look ahead adder reduces this delay by using more complex carry computation logic that significantly reduces logic levels for deciding all carry bits. Each carry bit becomes a function of cin and both carry-generation and carry-propagation conditions of all previous adder stages. Look to the example below for details.

``module carry_look_ahead_addr #(  parameter WIDTH = 8) (  input [WIDTH-1:0] a,  input [WIDTH-1:0] b,  input cin,  output [WIDTH-1:0] s,  output cout);  wire [WIDTH-1:0] sum, carry_generate, carry_propagate;  wire [WIDTH:0] carry_in_internal;   genvar i;  assign sum = a ^ b;  assign carry_generate = a & b;  assign carry_propagate = a | b;  assign carry_in_internal[0] = cin;  assign cout = carry_in_internal[WIDTH];generate  for (i = 0; i < WIDTH; i = i + 1) begin    assign carry_in_internal[i+1] <= carry_generate[i] | (carry_propagate[i] & carry_in_internal[i]);  endendgenerate  assign s = sum ^ carry_in_internal;endmodule``
``module CLA(a,b,ci,co,s); input [3:0]a,b; output [4:0]s; input ci; output co; wire [3:0]G,P,C; assign G = a&b; assign P = a^b; assign co=G[3]+ (P[3]&G[2]) + (P[3]&P[2]&G[1]) +  (P[3]&P[2]&P[1]&G[0]) + (P[3]&P[2]&P[1]&P[0]&ci); assign C[3]=G[2] + (P[2]&G[1]) + (P[2]&P[1]&G[0]) +  (P[2]&P[1]&P[0]&ci); assign C[2]=G[1] + (P[1]&G[0]) + (P[1]&P[0]&ci); assign C[1]=G[0] + (P[0]&ci); assign C[0]=ci; assign s = {co,P^C};endmodule``