In ripple carry adders the result delay is defined by a propagation delay of all carry line from the cin to the cout. This is if it is not pipelined. A carry-look ahead adder reduces this delay by using more complex carry computation logic that significantly reduces logic levels for deciding all carry bits. Each carry bit becomes a function of cin and both carry-generation and carry-propagation conditions of all previous adder stages. Look to the example below for details.
module carry_look_ahead_addr #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input cin,
output [WIDTH-1:0] s,
output cout
);
wire [WIDTH-1:0] sum, carry_generate, carry_propagate;
wire [WIDTH:0] carry_in_internal;
genvar i;
assign sum = a ^ b;
assign carry_generate = a & b;
assign carry_propagate = a | b;
assign carry_in_internal[0] = cin;
assign cout = carry_in_internal[WIDTH];
generate
for (i = 0; i < WIDTH; i = i + 1) begin
assign carry_in_internal[i+1] <= carry_generate[i] | (carry_propagate[i] & carry_in_internal[i]);
end
endgenerate
assign s = sum ^ carry_in_internal;
endmodule
Advantages:
The propagation delay is reduced so it provides the fastest addition logic.
Disadvantages:
The circuit is costlier as it needs more gates. The carry look-ahead adder circuit gets complicated if the number of variables and/or number of bits increase, so it becomes much more costly.