Verilog Wire?

Question

What is a wire in Verilog and how do I use it?

Answer 1

Wire - is the net data type and is for connecting elements. This is actually as a wire that connects points. And these points are outputs and inputs of the sequential or the combinational logic and may be determined as either explicit or implicit objects of reg data type. Logical conflicts from multiple sources of the same strength on a wire (or a tri net) result in x values. Driver values of 0 or 1 are always 'stronger' than the value of Z (which are to model the high-impedance state) and overdrives it, so 0-z will be 0, 1-z will be 1.

wire sdata;
assign sdata = sdata_io;
wire ncs_o = ncs_reg';
wire [31:0] busa;
assign busa = oe ? busa : 32'h0;

output sdata_io;
wire sdata_io;
assign sdata_io = oe ? sdata_reg : 1'bz;

Answer 2

Wires are like simple wires connecting two elements or ports to each other. In contrast to the reg variable, wires do not store values and do not retain their previous values. So continious assignment should be used for them.

The syntax is: wire "name";