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0 votes
in Verilog by (200 points)

What is wait in Verilog and how do I use it?

2 Answers

0 votes
by (240 points)

A wait statement is a form of the event control. It is used to delay an execution of a procedural statement until some condition becomes true. The nature of the wait statement is level-sensitive.

Syntax:

wait_statement ::= wait ( expression ) statement_or_null;

begin
wait (enable)
#10 c = 1'b1;
#10 c = 1'b0;
end
0 votes
by (240 points)

As the name shows,with the wait statement, the prorgram will wait until a statement becomes true. For example:

 wait (request==1)
out<= in_data;
It will wait until request becomes one and then sends the input data to the output.

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