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in Verilog by (220 points)

What are Verilog data types and how do I use them?

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There are two groups of data types: the variable data type and the net data type. These groups are different in the way that they are assigned, hold/store values, represent hardware structures. In simple terms, variables are combinational and sequenional logic (models of fabric elements) shuch are gates, flipflops etc. Nets are just nets or wires that connect the combinational and sequenional logic to each other.

Net types:

Wire - are for connecting elements. Logical conflicts from multiple sources of the same strength on a wire (or a tri net) result in x values. Drivers values of 0 or 1 are always 'stronger' than the value of Z (which are to model the high-impedance state) and overdrives it, so 0-z will be 0, 1-z will be 1.

wor - for wired or, look to the truth table
wand - for wired and, look to the truth table

Tri - are the same as wire net data type.

trior- for wired or, look to the truth table
triand - for wired and, look to the truth table
tri0 - are model nets with resistive pulldown devices on them. A tri0 net is equivalent to a wire net with a continuous 0 value of pull strength driving it.
tri1 - are model nets with resistive pullup devices on them. A tri0 net is equivalent to a wire net with a continuous 1 value of pull strength driving it.

Trireg - These nets are stores a value and are used to model charge storage nodes. A trireg net can be in one of two states:
Driven State - Is when at least one driver of a trireg net have a value of 0, 1, or x , the resolved value is the driven value of the trireg net.
Capacitive State - Is when all drivers of a trireg net are of value Z (that is to model the high-impedance), the trireg net hold its last driven value.

Uwire - are an unresolved wires that are used to model nets that allow only a single driver.

Supply nets:
supply0 - Are nets that used to model power supplies - GND. Supply0 drives 0 with the strange of supply0.
supply1 - Are nets that used to model power supplies - VCC. Supply0 drives 1 with the strange of supply1.

There no any difference between wire and tri net data types, so the use of such net data types are defined by designer in regards with designer's own purposes.

In practice I use only the wire net data type and in few cases I use the wand net data type (to model the 'wired and' of the I2C bus). I never use and never saw the use of such net data types as supply, trireg, tri, uwire. I beleave these types are not much useful in digital design.

I think, tri0 and tri1 might be useful, but I usually implement bidirectional port with tri-states using the wire net data type and sometimes added 'pull' strengths to assignments.

Examples of use:

inout sdata_io;
assign sdata_io = deata_output_enable ? data_o : 1'bz;

or the other one way may be:

assign sdata_io = !data_o ? 1'b0 : 1'bz;

In some cases the pull 1 driver may be added:

assign (pull1, pull0) sdata_io = 1'b1;

wand wired_and_line;
assign (pull1, strong0) wired_and_line = sorce0;
assign (pull1, strong0) wired_and_line = sorce1;
assign (pull1, strong0) wired_and_line = sorce2;

Regs (variables):

reg - The main variable data type to model both sequential and combinational logic. It is used for gates, flipflops, latches. Variables of this type can be assigned only in procedural assignment statements.

integer, real, realtime, time - Are bit higher level type than reg which mostly is 'hardware' type. These types are provided for convenience and to make the description more self-documenting. Both integer and real data types may be used instead of reg in some cases.

integer - is for 32-bit integer values
real - is for floating poit values
time - is for modelling time, this data type is typically used with $time system function
realtime - is for storing time as a floating point value.

Vectors

A net or reg may be declared as a vector by specifying a range. The range specification gives addresses to the individual bits in a multibit net or reg. Both left-hand value and right-hand value in the range may be any integer value - positive, negative, or zero. The left-hand value of a range may be greater than, equal to, or less than the right-hand value. By defaults vectors are unsigned. To define a signed vector need to declare it with the signed keyword.

examples:
wire [7:0] busa; // 8-bit bus
tri [31:0] busb; // for example tri may be use to tri-state buses, so this is a 32-bit tri-states bus.
reg [15:0] rega; // 16-bit register, latch, or bulk of gates
reg signed [63:0] regb; // the same as previous but marked as a signed, i.e. the MSB (left-hand) bit is a sign and the value is in the two's complement format

Arrays

Arrays are ordered and ranged groups of elements of the same type. Elements of array may be accessed only by a single index, not by range. The type of elements may be scalar as well as vector. Arrays are declared by specifying the element address range(s) after the declared identifier. Each dimension is represented by a range. Both left-hand value and right-hand value in the range may be any integer value - positive, negative, or zero. The left-hand value of a range may be greater than, equal to, or less than the right-hand value.

Arrays are used to declare memory, groups of buses, sets of constants, independent channels lines, and so on - for all that are homogeneous but shouldn't be mixed.

examples:
reg [7:0] memory [0:127]; // the 128 bytes memory;
wire [31:0] buses [0:3]; // 4 of 32-bit buses.
reg single_bit_matrix [0:15] [0:31]; // 16x32 matrix or two-dimensional array of single-bit registers

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by (240 points)

In one way it is divided to 2 class of data types, one is NET (wire) and reg. The former is used for interconnecting elements and the latter retains the value of the variable unitll a new value is assigned to it. On the other side, data types of integer, string, events, time and real

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