Verilog Include?

Question

What is a Verilog include and how do I use it?

Answer 1

This is the file inclusion compiler directive that is used to insert the entire contents of a source file in another file during compilation. The `include compiler directive can be used to include global or commonly used definitions and tasks without encapsulating this code to a module.

`include "prescaler_cfg.h"
`include "ultradibro_config.h"
`include "fifo_parameters.h"

Answer 2

It is a command to add a Verilog source file (headers) or verilog modules or components to the current file. Sytntax:

`include "filename"