Verilog Greater Than and Less Than?

Question

What are the symbols for greater than and less than in Verilog and what are some examples of syntax?

Answer 1

greater than: >
less than: <

for (i = 0; i < N; i = i + 1) begin ... end
if (received > expected) error_code <= overlap;
assign count_en = counter < border;

Answer 2

">", ">=", "<","<=" are the signs for greater than, greater than or equal, less than and less than orequal. We can use it both for logic or conditional statements. For example (Comp= A>B, the value for Comp will be 1 or 0) or if (A>B).