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0 votes
in Verilog by (220 points)

How do I implement a JK flip flop in Verilog?

2 Answers

0 votes
by (300 points)

Here's an example:

module jkfflop (
input j,
input k,
input clk,
output q,
output qn
);

reg ff;

always @(posedge clk) begin
case({j,k})
{1'b0,1'b0}: ff <= ff;
{1'b0,1'b1}: ff <= 1'b0;
{1'b1,1'b0}: ff <= 1'b1;
{1'b1,1'b1}: ff <= ~ff;
endcase
end

assign q = ff;
assign qn = ~ff;

endmodule
0 votes
by (300 points)

Module JKFF (input reset, clk, J, K, output Q)

always @(posedge clk, posedge rst) begin

if (reset)
Q <= 1'b0;
else
case({j,k})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b00: Q <= 1;
2'b00: Q <=~Q;
default Q <= Q;
endcase
end
endmodule

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