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0 votes
in Verilog by (220 points)

What is a ripple carry adder in Verilog and how do I use it?

2 Answers

0 votes
by (300 points)

This is a "base" scheme of an adder. And I think that this scheme is the best for speed up - by using pipelining. This is a set of full adders where the each full adder input Carry_in is the Carry_out of the previous adder. So full adders are chained in sequence by the carry line. Example:

module full_adder (
input a,
input b,
input cin,
output s,
output cout
);

assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (cin & b);

endmodule

module ripple_carry_adder #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input cin,
output [WIDTH-1:0] s,
output cout
);

genvar i;

wire [WIDTH:0] carry_line;
assign carry_line[0] = cin;
assign cout = carry_line[WIDTH];

generate
for (i = 0; i < WIDTH; i = i + 1) begin
full_adder full_adder_inst (
.a(a[i]),
.b(b[i]),
.cin(carry_line[i]),
.s(s[i]),
.cout(carry_line[i+1])
);
end
endgenerate

endmodule
I used pipelined ripple-carry-adders (as well as carry-save-adders) for addition, subtraction and multiplication when I need to use high frequency in ASIC design.
0 votes
by (300 points)

Ripple carry adder consists of a number of successive full adders. The number of FAs depends on the number of output bits. It is called ripple carry adder because the carry ripples from one FA to the next one. For example, for generating a 4-bit carry ripple adder you should first generate one Full adder using AND/OR and XOR gates and then instantiate 4 of these connecting the carry out of each FA to the carry-in of the next one.

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