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What is a latch in VHDL?

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VHDL Latch

Quick Syntax

Here's how to create a latch, which is not something you want to do:
PROC_LATCH : process (input_sel,input)
if input_sel = "00" then
output <= input(0);
end if;
end process;


Latches are a big no no in digital design. A latch can occur when these happen together:

1. You have an unclocked process
2. You have an output signal being set based on an input that is not guaranteed to occur all the time
3. You have not set the output signal under all conditions

In the example above, notice how the output only changes when input_sel is "00", but is not set for all other possibilities of input_sel. Plus, the process is unclocked. This meets are 3 criteria above.

Best Practices

1. Avoid latches, they are problematic in digital design.

2. Use clocked processes when possible, they help prevent latches and are better for timing performance on higher frequency designs. You will have to handle a 1 clock delay on the outputs of course.

3. Cover all of the logical possibilities. Use else's to do this in your statements where they are allowed, or set a default at the top of your process.
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