## VHDL Hex Values

### Quick Syntax

Hex in VHDL for 8-bits: x"00"

`signal my_slv : std_logic_vector(7 downto 0) := x"1F";`

........

my_slv <= x"0A";

### Purpose

Hex is a 16 based math system. Therefore, you can have these values:

Decimal => Hex:

0 => 0

1 => 1

2 => 2

3 => 3

4 => 4

5 => 5

6 => 6

7 => 7

8 => 8

9 => 9

10 => A

11 => B

12 => C

13 => D

14 => E

15 => F

In VHDL, hex is a much easier way to set bigger vectors instead of regular binary. This is because one symbol of hex is 4-bits of binary. For example:

`signal my_slv : std_logic_vector(15 downto 0);`

-- binary method
my_slv <= "0000000000000001";

-- hex method
my_slv <= x"0001";

You can also mix binary and hex for uneven 4-bit vectors:

`signal my_slv : std_logic_vector(9 downto 0);`

-- mixed method
my_slv <= "00" & x"01";