For Loop VHDL?

Question

How do you implement a for loop in VHDL?

Answer 1

VHDL For Loops

Quick Syntax

for Current_Range in Range_Start to Range_End loop
   new_signal(Current_Range) <= '1';
end loop;

Keep in mind that the above code is pointless since you could simply do this instead:
new_signal <= (others => '1');

So let's see why we would want to use for loops next.

Purpose

The purpose of the for loop in VHDL is to give you the ability to have a repeating loop that can be set to be implemented a discrete number of times. Unlike software, the for loop here is actually creating hardware implementations. So you need to be careful in how you use it because in FPGA land, we have limited hardware resources.

Because VHDL is so strict on type, usually for known designs where the width of signals is solid you may not need to ever use for loops. However, there are 2 very common reasons to use them:

1. When designing for re-usable code, for loops are an advanced way for the designer to make very modular code that can be quickly adapted to different signal widths. Here you can tie the range start and range end to either constants or better yet generics that can be changed quickly to alter the design.

2. It's a great way to create the same hardware design in a few lines of code where the alternative would require a ton of code for an equivalent design.

Example

In this example, we have an enable for each bit on a 64 bit bus, and if the enable is '1', then we pass the bus bit from input to output. If the enable is '0', we set the output bus bit to '0'. Basically, we are anding each input bus bit with the enable bit to create the output bus. This would take a ton of code to do without the for loop.

for i in 0 to 63 loop
   output_bus(i) <= input_bus(i) and bus_en(i);
end loop;

Which can be written this way too:

for i in 0 to 63 loop
   if bus_en(i) = '1' then
       output_bus(i) <= input_bus(i);
   else
       output_bus(i) <= '0';
   end if;
end loop;

Best Practices

1. For loops can be tricky depending on how you write them. Be sure to add comments on exactly what the goal is and how it works so that when you revisit your code later or if someone else needs to edit your code that it's easy to understand what's going on.

2. Be careful and aware of what the for loop is doing so that you aren't creating a design that uses a lot of resources needlessly.

3. Weigh the benefit of using for loops instead of long written code (15 lines or more) where for loops may make more sense and can be done in only a few lines.

4. Always shoot for re-usable code on common parts of the design, such that if you can have 1 design work for many situations, then consider for loops with generics driving the range so that it's easy to use the same design for multiple things.

5. Don't use for loops to look cute or advanced. Use regular and more common code most of the time when appropriate. Not everyone that will edit your code is a master and if they can't make your design work for something new, your design will die.

6. In my experience, I've probably used for loops 1% of the time. There needs to be a big savings in code to justify it.

Answer 2

A VHDL for loop is a construct that allows duplication of sequential code in a compact and generic manner.
It can be used instead of manually writing a more verbose code that has the same functionality.

Example :

for_loop : process ( INPUT_CLOCK ) is
begin
   if rising_edge ( INPUT_CLOCK ) then
       for index in 0 to 200
       loop
           some_signal ( index + 1 ) <= some_signal ( index ) ;
       end if ;
   end if ;
end process for_loop ;

Answer 3

A For Loop statement is a statement which includes a sequence of statements that is to be executed repeatedly for a defined number of iterations. The header of the loop specifies the discrete range for the loop parameter. In each loop step the parameter takes a value from this range, starting from it's leftmost value.

sample_scaled_loop: for i in 12 downto 0 loop
   if sample_delayed_tree_buf(i) = '1' then
       sample_scaled(i) <= sample_scaled_full_size(sample_scaled_full_size'high - (12-i));
   else
       sample_scaled(i) <= not sample_scaled_full_size(sample_scaled_full_size'high - (12-i));
   end if;
end loop;

function dif_triple (trireg : in triple_bit_array_t) return std_logic_vector is 
   variable v : std_logic_vector(trireg'range); 
       begin 
           for i in v'range loop 
           v(i) := (trireg(i)(2) xor trireg(i)(1)) or (trireg(i)(0) xor trireg(i)(1)) or (trireg(i)(2) xor trireg(i)(0)); 
           end loop; 
       return v; 
   end; 

function dif_triple_regs (trireg : in triple_reg_array_t) return reg_array_t is 
   variable v : reg_array_t(trireg'range); 
       begin 
           for i in v'range loop 
               v(i) := dif_triple(trireg(i)); 
           end loop; 
       return v; 
end function;

Almost all cases is to replicate the same actions to other parts of an object. And in testbenches - also is to repeat the same action the required number of iterations (for example to simulate transmission data to a channel).

Answer 4

The word loop clearly indicates that this is a tool used for repeating a specific portion of code over and over again. For loops can be used to repeat the iterations a specific number of times. A simplified syntax is given below:

for var in var_range loop
   ...statements;
end loop;

Here, var is a variable that has a specific range that is mentioned in place of var_range. The number of times the loop runs depends on that range. An example is:

for i in 1 to 10 loop
   report "i=";
end loop;