VHDL vs Verilog
I don't think one is better than the other, as they both have their pros and cons.
The biggest factor here is that VHDL is strictly type casted, which makes it harder to learn but less prone to bugs after synthesis and simulation. Bugs at that point are from wrong assumptions, incorrectly implemented logic, or not following good design practices.
Verilog is less strict and more software like in nature, which makes it easier to learn but much more dangerous to use in practice. Plus, there is controversy over the fact that Verilog has some non deterministic issues, see: https://insights.sigasi.com/opinion/jan/verilogs-major-flaw/
I usually like to see what the market thinks about questions like these, so a few indicators:
1. VHDL and Verilog have been nearly neck and neck over the past 10 years in the USA. At least at the beginning of 2020 they are still close and it looks like Verilog is slightly more popular, probably because of SystemVerilog.
2. Google keyword research (using Ahrefs) at the end of 1/2020 for the USA shows:
- VHDL is searched around 11,000 times each month
- Verilog is searched around 12,000 times each month
- There's volatility month to month of course
3. Your country matters as the popularity will be different. Europe favors VHDL while Asia favors Verilog. It's pretty split in the USA and India. This is all prone to change in the future.
4. Industry matters, ie defense vs auto vs manufacturing vs commercial
In order to choose which one to learn first, you need to first decide what your goals are for learning. If you want a job and career in this field, then figure out what industry you want to work in over the next 10 years and ask around to see what some of the top companies that you would like to work for are using. Find out what is the top preference in your specific country too. Go look at job postings to see which one is most frequently listed in the requirements section.
For example, in the USA defense industry, VHDL is still widely favored and used. Other industries might be different.
Keep in mind that most modern tools often allow mixed language source code files. That means you can have both VHDL and Verilog code used on the same design. However, you will really make your co-workers and boss angry if you use a different language than they do. In most places, you will be told which language to use.
If you are just a student wanting to play around with FPGA's, then you should probably dabble lightly in both so that you are aware of the basics. That will make you the most marketable in a job interview.