VHDL vs Verilog?

Question

Which language is better and which one should I learn?

Answer 1

VHDL vs Verilog

Comparison

I don't think one is better than the other, as they both have their pros and cons.

The biggest factor here is that VHDL is strictly type casted, which makes it harder to learn but less prone to bugs after synthesis and simulation. Bugs at that point are from wrong assumptions, incorrectly implemented logic, or not following good design practices.

Verilog is less strict and more software like in nature, which makes it easier to learn but much more dangerous to use in practice. Plus, there is controversy over the fact that Verilog has some non deterministic issues, see: https://insights.sigasi.com/opinion/jan/verilogs-major-flaw/

Demand

I usually like to see what the market thinks about questions like these, so a few indicators:

1. VHDL and Verilog have been nearly neck and neck over the past 10 years in the USA. At least at the beginning of 2020 they are still close and it looks like Verilog is slightly more popular, probably because of SystemVerilog.

2. Google keyword research (using Ahrefs) at the end of 1/2020 for the USA shows:
- VHDL is searched around 11,000 times each month
- Verilog is searched around 12,000 times each month
- There's volatility month to month of course

3. Your country matters as the popularity will be different. Europe favors VHDL while Asia favors Verilog. It's pretty split in the USA and India. This is all prone to change in the future.

4. Industry matters, ie defense vs auto vs manufacturing vs commercial

Purpose

In order to choose which one to learn first, you need to first decide what your goals are for learning. If you want a job and career in this field, then figure out what industry you want to work in over the next 10 years and ask around to see what some of the top companies that you would like to work for are using. Find out what is the top preference in your specific country too. Go look at job postings to see which one is most frequently listed in the requirements section.

For example, in the USA defense industry, VHDL is still widely favored and used. Other industries might be different.

Keep in mind that most modern tools often allow mixed language source code files. That means you can have both VHDL and Verilog code used on the same design. However, you will really make your co-workers and boss angry if you use a different language than they do. In most places, you will be told which language to use.

If you are just a student wanting to play around with FPGA's, then you should probably dabble lightly in both so that you are aware of the basics. That will make you the most marketable in a job interview.

Answer 2

"Which is better" is somewhat subjective. So instead of answering directly - I'll list the pros of each as I see them.

VHDL pros :

1. Strict and strongly typed - I view this as an advantage as this may lead to more verbose code but at the same time prevent bugs in the code. Compiler warnings and errors are your friends, not enemies.
2. Used often in FPGA designs.
3. Taught a lot in school - most Electrical Engineering graduates will have some background in it.
4. Very common in the defense industry.

Verilog pros :

1. Less verbose than VHDL. Allows to do the same with less lines of code.
2. The dominant language in ASIC design. Virtually NO ASIC design is done in VHDL.
3. Based on C - so it's easier to understand if you already have some software background.
4. System Verilog is the future and it's based on - and backward compatible with Verilog. As an Engineer you always have to worry about "future proofing" yourself and the fact that System Verilog is getting more support ( while VHDL stagnates ) is a major advantage.

Answer 3

It depends on what you need to do and how you like to do it. The good way is to learn both and make choices based on the task and your experience. I started with VHDL.

If the choice between VHDL and Verilog (i.e. not SystemVerilog). VHDL has a better type system with user defined types and a big bulk of object's and type's attributes to control and handling ranges, borders and so on. It has good optionis such as packeges to encapsulate a common and reusable functionality in external switchable source code. The one big advantage is that synchronous/asynchronous logic defines only by statements and never by type of objects (as reg and wire in Verilog). But this languadge is more verbose as it's ancestor - ADA. VHDL is more academic than Verilog.

Verilog has good abilities of preprocessor (it is really useful, especially in configuration of modules). It is much less verbose than VHDL. Also it has adnvantages in verification as an accsess through a modules hierarchy. More comfortable objetcs declaration (not in strictly defined place) and initialization. Verilog is good if you want to hard code design based on a low level data representation and which works well with script paramaterization. This would be more convenient if you have a detailed specification down to low level. But if you need a more formal rtl - you need VHDL with it's hard structure of entity architectures, packages, user defined types, operator overloading etc.

And a little about SystemVerilog. This language has got a lot of advantages of both languages: packages, user defined types and structures, shorter Verilog syntax, various ways to parameterize modules using both module parameters and preprocessor `define-directives, statement-defined choice between synchronous/asynchronous logic when using logic instead reg/wire. Also, it has a really good verification subset (PRNG, classes, process flow control), so it can be used instead of such an instrument like SystemC.

Answer 4

The VHDL language needs more words to do the same thing than Verilog and it is a strongly typed language. Strict definitions of data types exist and all variables must be defined with a particular data type.

Verilog is similar to C and requires fewer lines of code. It is quite good for hardware modeling. The choice of the language comes down to personal preference as there is not a very clear or defined superiority of one language over the other.