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in VHDL by (200 points)

What is VHDL 'when else' and how do you code it?

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by (1.8k points)

VHDL When Else

Quick Syntax

output <= input1 when mux_sel = "00" else
input2 when mux_sel = "01" else
(others => '0');

Purpose

The when else statement is a great way to make a conditional output based on inputs. You can write equivalent logic using other options as well. It's not to be confused with the when used in a case statement.

In my experience, many people use the when else to make a concurrent mux. In fact, this is so common it should become one of your most basic tools in coding VHDL. Keep in mind that most synthesis tools will look at the output signal and the input signals and see what clock domain they are on, such that timing constraints will apply.

You should make sure that both inputs and output are on the same clock domain, assuming it's relevant to your design, or if not, make sure that your constraints take that into account. Otherwise, most likely the tools will put levels of logic in between clocked parts of your design and you might run into routing problems to meet timing.

Another important note, when else isn't allowed inside a process prior to VHDL-2008. So if you "must" have it in a process, you need to make sure that your tool chain supports 2008 and that it's turned on for that part of your design source.

Best Practices

1. Use when else for muxes as they are clean, clear, and easy to modify.

2. Watch out for different clock domains of inputs and output and remember that you are pushing levels of logic that the tools have to get through to meet timing. For high frequency designs, this might be a bad idea. Instead for high frequency, you might consider a more traditional clocked process option that gives the tools more leeway on routing.

3. Make sure all states of your conditional signal are covered. Usually adding an else others at the end is a great idea in case someone in the future removes one of the options so that it won't generate a bug.

4. Try to only use when else outside a process even though it's supported in VHDL-2008. Why? Because in 2020, some synthesis tools still have some bugs compiling VHDL-2008. Perhaps in the future this won't be an issue. Plus, if you have to support an older FPGA using older tools, you won't have 2008 as an option. Keep these issues in mind when you code. There are better options than when else if you need to have it in a process, like using case instead.
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by (700 points)

The VHDL "when else" statement is a way to write conditional code in a compact single line manner.

Example :

leap_year <= '1' when year = 2020 else '0' ;

0 votes
by (700 points)

This is the same thing as if-else but a concurrent statement (i.e. not inside a process in VHDL code). Using for conditional signal assignments and could be used for MUX as an example:

o <= in0 when sel = "00" else 
in1 when sel = "01" else
in2 when sel = "10" else
in3;
0 votes
by (700 points)

When else is a conditional statement in VHDL. It is used for conditional assignment. The use of this is illustrated in the implementation of MUX in one of the previous questions. Here is another example to explain when-else:

y <= "100" when x = "00" else 
"010" when x = "01" else
"001" when x = "10" else
"101" when x = "11";
The value assignment to variable 'y' is dependant on the value of variable 'x'. The assignments depend on the condition of variable x.

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