type type_array_slv is array (0 to 31) of std_logic_vector(7 downto 0);
signal my_bus : type_array_slv;
signal your_bus : type_array_slv;
-- pass one 8-bit vector from one array to another
your_bus(0) <= my_bus(1);
-- pass bit 1 from array 0 of my_bus to bit 1 of array 31 of your_bus
your_bus(31)(1) <= my_bus(0)(1);
Arrays in VHDL are a handy way to put together a more complex group of signals. They are often found when making busses. There are many options on how you can use them, so it will come down to personal preference.
Typically, arrays will be bounded, but you can have unconstrained arrays in cases where you want to have multiple different sizes of the same type of array.
Keep in mind that not all coders will understand the more advanced ways of using arrays, so you might want to consider keeping it more simple here to make sure that your code is maintainable.
Here is how to code a VHDL array of std_logic_vector, in this case 64 sets of 16-bit vectors:
type type_array_slv is array (0 to 63) of std_logic_vector(15 downto 0);
signal bus_64x16 : type_array_slv;
-- grab the 32nd std_logic_vector
output <= bus_64x16(31);
-- grab the 32nd std_logic_vector, 16th bit
output_bit <= bus_64x16(31)(15);
Here is how to code a VHDL array of integers, in this case 64 sets of 0-15 integers:
type type_array_int is array (0 to 63) of integer range 0 to 15;
signal bus_64xint : type_array_int;
-- grab the 32nd integer
output <= bus_64xint(31);
You can leave off the "range 0 to 15" above if you want the full spectrum of integers.
Here is how you can use unconstrained arrays for multiple different sizes of the same type:
type type_array_int is array (integer range <>) of integer;
signal bus1_16xint: type_array_int(0 to 15);
signal bus2_32xint: type_array_int(0 to 31);
1. When using arrays, make sure and properly name the type so that it represents the bounds of the array. In some designs, you could have multiple types which can lead to a lot of confusion. By properly naming each type to represent its size, it greatly reduces problems.
2. When naming signals that are created from an array type, it's a good idea to indicate size limits in the signal name so that the designer will know by looking at the signal name what the array represents.
3. Always put good comments about what each dimension of the array is for so that it is clear.
4. Properly bound the array when it's known.