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VHDL function, what is it and how do you use it?

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VHDL Functions

Quick Syntax

function translate_xy(x : in integer;
y : in integer) return integer is

variable output : integer := 0;
begin
output := x + y + 25;
return output;
end function;

Purpose

Think of a function in VHDL as something that you give multiple inputs and it returns an output based on those inputs. If you need multiple outputs, check out procedures.

Functions are a nifty way to have common source code in one place that can be called from any other source code. If you find yourself doing the same kind of logic repeatedly throughout a design, then it's a good idea to make a function out of it.

What the pros do is usually have some sort of common_pack.vhd file or similar where they use it as a package that can be called by any other VHDL source file that needs to use any of the functions in that package. It's a great way to be able to bring in existing capability into new designs that can be used throughout the source files.

You can get as fancy as you want and break groups of functions into different package files that can be used with different sets of other source code. For example memory related functions with memory source code. However, that gets complicated and may be prone to errors for people that don't know where which functions are in which files. The common file approach usually works better.

Examples

Here's an example package file where you can have your functions:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package common_pack is

function translate_xy1 (x : in integer;
y : in integer) return integer;

function translate_xy2 (x : in integer;
y : in integer) return integer;

end package common_pack;

package body common_pack is

function translate_xy1 (x : in integer;
y : in integer) return integer is

variable output : integer := 0;
begin
output := x + y + 25;
return output;
end function;

function translate_xy2 (x : in integer;
y : in integer) return integer is

variable output : integer := 0;
begin
output := x + y - 25;
return output;
end function;

end package body common_pack;
And here's how you call it in the source file that you need to use the functions, assuming you compiled the package in library "work":
library work;
use work.common_pack.all;
And here's how you use the function in your code:
constant TRANSLATE_TO_Z : integer := translate_xy1(3,4);

Best Practices

1. If you do similar things often, capture it in a function.

2. For functions that are commonly used across multiple designs, put them in a common package file that can be used again.

3. Make sure your functions account for all possibilities of its inputs, and make the output initialized to a known value just in case.
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by (700 points)

A VHDL function is a structure that can group non-sequential operations under a single call. Their use in synthesizers is usually limited to describing combinatorial logic. They are used to make the code more compact and improve re-usability. Example :

function count_ones -- declaration
(
    input : std_logic_vector
)
return natural is
variable counter : natural := 0 ;
begin

for index in input ' range
loop
if input ( index ) = '1' then
counter := counter + 1 ;
end if ;
end loop ;
return counter ;

end function ;

number_of_ones <= count_ones ( input ) ; -- usage
0 votes
by (700 points)

The VHDL function is a subprogram that either defines an algorithm for computing values or describes some behavior. Functions return values of specified type (scalar or complex) and the function call is an expression.
Functions can be either pure (by default) or impure. Pure functions always return the same value for the same parameters, but the result of impure functions may differ for the same parameters. An impure function may have side effects: like updating objects outside of their scope, it may be when it works with file systems for example.

I use it when I need to reuse the same computations or behavior in several places and/or modules/entities. Moreover, there is something like an encapsulation advantage if we would look at VHDL packages like a kind of class.

For example, I need to add an ability to switch on/off a Triple Modular Redundancy (TMR) as a Self Restoring Logic (SRL). I can use a set of types and corresponding functions to construct objects of these types, extract a data from these objects, and perform TMR on these objects. I can switch it either on or off or change it for other SRL types by just changing these functions and types. Then I can use these objects and functions to code my VHDL model, which could be configured from the package to either use SRL or not.

Here is a simple example of a function:

function integer_log2(v : in natural) return integer is
variable log2count : integer := 0;
variable x : integer := v;
begin
while x > 1 loop
log2count := log2count + 1;
x := (x + 1) / 2;
end loop;
return log2count;
end function integer_log2;
I used this function to define an array range in a port declaration.
entity ram_sp_generic is
generic (
ram_size : integer := 2048;
ram_data_width : integer := 40;
use_rden : boolean := false);
port (
clk_i : in std_logic
d_i : in std_logic_vector(ram_data_width-1 downto 0)
q_o : out std_logic_vector(ram_data_width-1 downto 0)
a_i : in std_logic_vector(integer_log2(ram_size)-1 downto 0)
rden : in std_logic
wren : in std_logic);
end entity;
0 votes
by (700 points)

Functions are subprograms and can have multiple inputs or no input at all. However, a function in VHDL always returns a value. Furthermore, you cannot use a wait statement in a function. Functions can be of two types: pure or impure. A pure function is the one that can neither read nor modify any external signal, hence, whenever it is called, it always returns the same value. The following syntax can be used to declare a function in VHDL:

[pure|impure] function function_name ( var1_name : var1_type := default_value;
var2_name> : var2_type := default_value;
... )
return return_type is
<constant_or_variable_declaration>

begin
code_statements
return value
end function;

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