Full Adder in VHDL?

Question

What is a Full adder, and how do I do it in VHDL?

Answer 1

A full adder is a circuit thats able to accept 2 bits and a carry bit as input and output the result and a carry bit.

Example :

signal carry_in , a , b , carry_out , result : std_logic ;

result <= a xor b xor carry_in ;
carry_out <= ( a and b ) or ( carry_in and a ) or ( carry_in and b ) ;

Answer 2

A Full adder is a single bit wide adder with a carry. Something like this:

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
  port(
    A : in STD_LOGIC;
    B : in STD_LOGIC;
    CIN : in STD_LOGIC;
    C : out STD_LOGIC;
    COUT : out STD_LOGIC
  );
end entity;

architecture rtl of fulladder is

begin

  C<=A xor B xor CIN;
  COUT<=(A and B) or (B and CIN) or (A and CIN);

end architecture;

Answer 3

Full Adder has three inputs and two outputs. The inputs are one-bit binary numbers, a1, a2 and cin (carry-in). The outputs are also one-bit binary numbers, sum and c_out (carry out). We can say that full adders add three binary numbers and outputs the sum and the carry. Its implementation is a combination of two XOR gates, two AND gates and one OR gate. The truth table is such that when an odd number of inputs are 1, the sum is also one and c_out is 1 when two or more inputs are 1. VHDL code for full adder is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
  Port ( 
  a1 : in STD_LOGIC;
  a2 : in STD_LOGIC;
  cin : in STD_LOGIC;
  sum : out STD_LOGIC;
  C_out : out STD_LOGIC);
end full_adder;

architecture gate_level of full_adder is
 begin
   sum <= a1 XOR a2 XOR cin ;
   c_out <= (a1 AND a2) OR (cin AND a1) OR (Cin AND a2) ;
 end gate_level;